Computer and indicator system



Aug. 4, 1959 F. G. STEEL E 2,898,040

COMPUTER AND INDICATOR SYSTEM Filed Sept. 26, 1952 6 Sheets-Sheet 1 bl-pmzcrmm e a5 47 QQANTIZEE L PARALLEL c axon/mark BI-Dnzscnoml Floyd 6. Sfee/e BY TTORNEY' Aug. 4, 1959 TIMING SIGNAL sol/2C5 F. G. STEELE COMPUTER AND INDICATOR SYSTEM Filed Sept. 26, 1952 6 Sheets-Sheet 2 ATTOIHVEY Aug. 4, 1959 F. G. STEELE COMPUTER AND INDICATOR SYSTEM Filed Sept. 26, 1952 6 Sheets-Sheet 5 gomcrsc CONTACTS B cola/m (rs A IDLE co/vrAcrs g I e 3 5 m. 0 U! A0 HF B N w r, #J NH 5 HM 6. 1H I J+ H.

ATTORNEY Aug. 4, 1959 STEELE 2,898,040

COMPUTER AND INDICATOR SYSTEM 6 Sheets-Sheet 4 Filed Sept. 26. 1952 INVENTOR.

I Player G. Sfee/e CALM Aug. 4, 1959 F. G. STEELE COMPUTER AND INDICATOR SYSTEM 6 Sheets-Sheet 5 Filed Sept. 26, 1952 INTERVALS INVENTOR. Floyd 6. 5f'ee/e 9 m TIM/N6 SIGNAL fffIIIIII JULJULFILJ I 2 3 4 5 6 7 8 9 I0 I/ l2 /5 M I5 I6 17/8 TIM/N6 INTEEVALS M. NH 7 m HIM m. 4 m

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m H n m m n W M U m H V m m MEW m;umwm---l [III-- Aug. 4, 1959 F. G. STEELE COMPUTER AND INDICATOR SYSTEM 6 Sheets-Sheet 6 Filed Sept. 26, 1952 INVENTOR Floyd 6. 5fee/e T1 RNEY United States atent 2,898,040 Patented Aug. 4, 1959 COMPUTER AND INDICATOR SYSTEM Floyd G. Steele, La Jolla, Calif., assignor to Digital Control Systems, Inc, a corporation of California Application September 26, 1952, Serial No. 311,609

39 Claims. (Cl. 235-151) This invention relates to a displacement computer and indicator system, and more particularly, to a computer and indicator system using electrical signals in di-function form for computing and indicating the relative angular displacement between two rotating shafts.

Two principal types of electronic computers have been developed in the past. The earliest and most widely known is the analogue type in which computational information is generally represented as a magnitude; for example, as an analogue potential. When used for control purposes, for example, this information may relate to some function of a moving object, such as the displacement, velocity, etc., thereof. The computer continually compares this information analogue signal with a standard potential, the magnitude of the standard potential representing the precise displacement, velocity, etc. desired for the object. The comparison process, in turn, produces an error signal whose magnitude represents the divergence between the objects existing function and that desired for it, and is utilized by the computer to control the particular function of the object so as to maintain the error signal at a minimum value. With this accomplished, a close correlation is continuously maintained between the existing and the desired displacement, velocity, etc.

This analogue type of control may be readily effected, for an average control problem, without excessive circuitry. However, the basic difficulty arising in analogue systems is that of securing sufiicient accuracy of control. As is well known, such accuracy is dependent not only upon continuous and uninterrupted operation of the com puter components, but upon the inherent accuracy, under the best possible operating conditions, of these components, especially those associated with the potentialstand- .ard. Attempts to increase this accuracy have resulted in extremely elaborate circuitry with the ensuing high cost,

difficulty of servicing, and decreased reliability.

On the other'hand, the other and more recent type of electronic computer has been that of numerical, and in particular, binary computers. In the binary type of computers, for example, information is represented electrically in the form of binary numbers and exact accuracy of each numerical computation is thus ensured owing to the precise nature of the mathematical operations involved. Also, since the information is represented in numerical form, great overall accuracy of control is obtainable since each piece of information may be represented to a very high degree of accuracy by forming each binary number corresponding thereto with a relatively large number of place digits.

A basic factor contributing to the recent advance of binary computers, other than the high degree of com- :putational accuracy obtainable therein, is the fact that Ithe binary digit values of and 1 may be quite readily represented by the two output voltage levels of a bistable flip-flop. By employing such flip-flops in conjunction with and and or gating circuits, only these two out- ;put voltage levels need to be utilized in the entire computer system, and extremely complex associations be tween various gating circuits and groups of flip-flops may therefore be formed without undue difliculty. Also, owing to the numerical type of computation, the accuracy of the computational results will not be affected in any way by reasonable variations of these voltage levels. Thus, the potential standard, which contributes one of the limiting factors in the output accuracy of analogue computer systems, is completely unknown in binary computers.

Binary computers have several basic disadvantages which severely limit their practical applications. These limitations arise principally from the nature of the binary numbers employed to represent the information to be operated on. In the first place, the value of each binary number is determined by the value of its individual place digits. Each place digit of a binary number contributes, however, an entirely different value to the final overall value of the binary number than do any of the other place digits thereof. For example, the twos place digit has exactly twice the value in a binary number of the units place digit and in turn, has only one-half the value of the fours place digit of the same binary number.

Owing to this property of binary numbers, considerable circuitry must be provided in a computer system for merely keeping track of the binary digits in each number, since the interchange of any pair of place digits having opposite values will obviously cause considerable computational error. This is especially true in performing arithmetic operations between two binary numbers in which basic arithmetic operations must be performed only between corresponding place digits thereof.

Furthermore, since the higher place digits of a binary number have a greater relative value than do the low place digits thereof, any reversal of a single value thereof, owing to an intermittent component failure, for example, will produce inaccurate computational results. Also, since negative as well as positive binary numbers must be employed, additional circuitry is required to designate the sign of each binary number as well as of the binary numbers resulting from arithmetic operations performed by the computer between other binary numbers.

All of the above stated factors have, with other factors not mentioned, necessitated extremely complex and involved circuitry for even the most simple of binary computers. Such computers may involve, at the barest minimum, several hundred vacuum tubes, with thousands of associated diodes, resistors, capacitors, etc. Oftentimes the failure, either permanent or intermittent, of a single component will cause complete inaccuracy in the computational results. Thus, not only is the initial cost of such computers extremely high, but the servicing thereof, in-

' cluding the loss of operational time owing to such component failure, is likewise extremely high.

Another factor, inherent in representing information in binary number form which tends to limit the utility of binary computers for control applications, apart from the circuit complexity thereof, is the mamier in which the information, forming the basis of the control, must be acquired. Some function such as displacement, velocity, etc. of a moving object to be controlled may be continuously indicated by a potential, a frequency, etc. However, the binary number representing the particular functiornmust be derived from the potential, frequency, etc. at a given instant of time and hence only represents the function at that instant of time. The resultant binary number is in turn processed by the computer and the computcrs output signal, representing a binary number, is transformed into a corresponding control signal, which in turn, is used for controlling the object. This control process is then repeated at a later instant of time by again deriving a binary number representing the objects new velocity, displacement, etc. and repeating the computation and control processes. In this way, the ob ect is controlled at discrete, spaced instants of time in accordance with binary numbers also derived from it at discrete, spaced instants of time.

The control is thus only intermittent in nature, that is, between the instants of deriving binary numbers, the computer has no means of determining the actual operation of the object under control. Thus, any change of control to be applied to the object, must necessarily be delayed until after the next computational operation with the result that appreciable errors may exist in the function of the controlled object before correction can be applied thereto. Often, excessive computational speeds must be employed in order to shorten the interval between information samplings.

The device according to the present invention transforms information into a radically new and different nonnumerical electrical form suitable for new types of computational and control processes. The character of this non-numerical form of information is capable of, when considered for computational control purposes, alleviating a majority of the disadvantages existent in digital and analogue computers as noted above while yet retaining the inherent simplicity of analogue computers and the inherent accuracy of binary computers. In particular, this non-numerical type of information is represented by an electrical signal in, as defined, di-function form. A signal in di-function form or, as is later designated, a di-function signal, comprises a series of alternate high and low voltage levels of the type produced by flip-flops, for example, each of the voltage levels appearing for an integral number of timing intervals, the timing intervals being electrically indicated by a clocking or timing signal.

A high voltage level appearing for one timing interval represents, by definition, an instantaneous di-function value of +1 and a low voltage level appearing for an interval represents an instantaneous di-function value of l. The ordinary or average value represented by a di-function signal, as contrasted with an instantaneous value, must be considered over an integral number of consecutive timing intervals during a period of time, and is defined as the ratio between the number of timing intervals during the period that the signal is at its +1 value minus the number that the signal is at its 1 value to the total number of timing intervals during the period.

This definition may be represented most conveniently in mathematical form by the equation:

NJ is the number of timing intervals during the period that the difunction signal is at its high voltage level or +1 value;

N is the number of timing intervals during the period that the di-function signal is at its low voltage level or 1 value;

N +N is the total number of timing intervals of the period; and

V is the average represented by the di-function signal during the given period of time.

As is apparent, the value of a di-function signal will vary in accordance with the length of the timing period over which it is considered, and the accuracy with which any given piece of information maybe represented in difunction form will, in general, be proportional to the number of timing intervals used to represent it.

In considering further the character of information expressed in di-function signal form, it is apparent that both positive and negative values may be readily represented by generating a greater or less number, respectively, of +1 values than are 1 values. Also, the di-function value of zero is readily available in the form of alternate instantaneous +1 and -l values appearing during consecutive timing intervals. This latter concept of a zero valued di-function signal is a fundamental one which is used extensively by the system of the present invention.

In considering now, the fundamental difference in representing information in di-function form and in binary number form, as particularly directed toward computational control problems, it is apparent that any given instantaneous di-function value of a signal will contribute the same relative value to the average of the signal, as considered over a period of time, as will any other instantaneous di-function value occurring during the same period. Hence, no particular order of +1 and 1 values need be observed in a di-function signal in order to have it represent any desired piece of information. The only requirement that must be observed is that a correct relationship between the relative number of each is obtained so that the desired average be had. Furthermore, any inaccuracy of a single instantaneous (ii-function value, owing to an intermittent component failure, for example, will cause only a slight error in the final di-function value considered over a period of time and will hence, not lead to overwhelmingly inaccurate computational results.

Another important fundamental difference between difunction and binary information lies in the fact that the value of a di-function signal, representing some function of a moving object, for example, will respond instantaneously to changes in magnitude of the objects function. This is accomplished by generating a greater relative number of either instantaneous +1 values or instantaneous 1 values, respectively, as determined by the initial relationships set forth between the functions magnitude and the value of the di-function signal.

Although the computer and indicator system of the present invention is closely related to, but not specifically concerned with computational control problems, the circuitry and operation of its components will enable one skilled in the art to readily appreciate other advantages not specifically set forth here of di-function over binary information. In particular, the computer and indicator system of the present invention includes a component for generating a di-function signal, a component for performing an arithmetic operation on a pair of di-function signals, a component for deconvcrting the information contained in a di-function signal into information in pulse form, and a component for counting the resultant pulses. Additional properties of di-function signal information will be apparent in the specific descriptions directed to the above noted components as set forth later in this disclosure.

More particularly, the computer and indicator system of the present invention includes first and second identical di-function bi-directional angular quantizers responsive to first and second variables, which are for the purposes of the explanation of this invention, first and second rotating shafts, respectively. Each quantizer normally produces a di-funetion output signal having an average value of zero, that is, alternate +1 and 1 instantaneous di-function values. However, each quantizer, upon each predetermined magnitude of rotation of its respective shaft ina designated positive direction, generates an extra +1 value in its output di-function signal, that is a +1 value appearing for two consecutive timing intervals. On the other hand, each quantizer produces an extra 1 value in its output signal, that is, a 1 value appearing for two consecutive timing intervals upon each corresponding magnitude of rotation of its respective shaft in its opposite or designated negative direction.

The next component included in the system is a difunction parallel half-adder or averager, hereafter termed half-adder, which normally receives two input di-function signals and produces an output di-function signal the value of which is one-half the value of its two input signals. Although the half-adder is derived by considering it as a half-adder, the arithmetic process of di-function subtraction is required in the computer and indicator system and is readily obtained by the simple expedient of adding the first quantizers output signal to the second quantizers complementary output signal. The average value of the adders di-function output signal thus represents the difference between the average values of the two input difunction signals and, in a manner similar to its pair of input signals, normally contains alternate +1 and 1 values representing the di-function value of zero. However, upon the appearance of a pair of extra +1 values or extra 1 values in either of its input signals, only one extra +1 or +1 value, as the case may be, is generated by the half-adder in its output signal owing to its averaging properties.

The output signal from the half-adder component is applied to a deconverter, the deconverter acting to produce a signal on one of its two output conductors each instance the half-adders output signal contains an extra +1 value and a signal on its other output conductor each instance the adders output signal contains an extra 1 value.

The two output conductors of the deconverter are coupled through two differentiating circuits, respectively, to two input terminals of a conventional binary up-down counter. The counter responds to pulses appearing on one of its input terminals for counting up in binary digit steps of one and responds to pulses appearing on its other input terminal for counting down in binary digit steps of one. he magnitude of the count indicated by the counter numerically represents the difference in the angular displacement between the first and second shafts and the sign of the count indicates the direction of this displacement.

In addition to the bi-directional quantizer illustrated, there is also set forth a uni-directional di-function angular quantizer for converting the rotation of a shaft, rotatable in one direction, into a corresponding di-function signal. This latter signal contains extra +1 di-function values for each predetermined amount of shaft rotation.

It is therefore, the principal object of the present invention to provide a system for computing and indicating the relative angular displacement between two rotating shafts.

Another object of the present invention is to provide a device for computing and indicating the relative movement between two movable members.

A further object of the present invention is to provide a device for computing and indicating the magnitude and direction of displacement between two moving members, each of the members having movement in two directions.

A still further object of the present invention is to provide a device utilizing signal information in di-function form for numerically indicating the magnitude and direction of movement between two movable members, each of the members having movement in two directions.

Another object of the present invention is to provide a device for producing a di-function signal, the value of which represents the difference in movement between two movable members, and numerically indicating the value of the di-function signal.

Another object of the present invention is to provide a device for computing and indicating the relative angular displacement between two rotating shafts, each of the shafts being rotatable in two directions, by electrical signals in di-function form.

Another object of the present invention is to provide a device for producing an output signal in di-function form, the value of which represents the movement of a movable member.

A further object of the present invention is to provide a quantizer for use with a movable member, said quantizer producing a di-function signal the value of which represents over a given period of time the displacement of the movable member during the period of time.

Still another object of the present invention is to provide a quantizer for use with a member having two directions of movement, said quantizer producing an output (ii-function signal the value and sign of the value of which represent the magnitude and direction, respectively, of the movement of the movable member.

A further object of the present invention is to provide a quantizer for indicating the direction and magnitude of movement of a movable member having two paths of movement by a pair of complementary di-function signals.

Another object of the present invention is to provide a device for use with a movable member, said device normally producing alternate high and low output voltage levels during consecutive timing intervals but responsive to each predetermined magnitude of movement of the member for producing one of said output voltage levels for two consecutive timing intervals.

Still another object of the invention is to provide a device for use with a movable member having first and second directions of movement, said device producing alternate high and low voltage levels during consecutive timing intervals but responsive to a predetermined magnitude of movement of the movable member in said first and second directions for producing said high and low voltage levels, respectively, for two consecutive timing intervals.

A further object of the present invention is to provide a device for averaging the values of a pair of difunction signals.

A still further object of the present invention is to provide a device for adding a first di-function signal to a second di-function signal and producing a third difunction signal whose di-function value is one-half the sum of the di-function values of the first and second signals.

Still another object of the present invention is to provide a parallel di-function half-adder for producing an output di-function signal whose value is the average of two input di-function signals.

Another object of the present invention is to provide a device for producing a high output voltage level in response to the simultaneous appearance of a high voltage level in each of two input signals and a low voltage level in response to the simultaneous appearance of a low voltage level in each of the two input signals, and alternate high and low voltage levels in response to the simultaneous appearance of different voltage levels in the two input signals.

Still another object of the present invention is to pro vide a device for producing an output di'function signal representing one-half the difference in di-function values of a pair of input signals.

A further object of the present invention is to provide a device for adding a first di-function signal to the complementary signal of a second di-function signal to produce an output di-function signal whose value is a function of the difference in values between the first and second di-function signals.

Still another object of the present invention is to provide a device for converting the information contained in a di-function signal into pulse form.

Another object of the present invention is to provide a device for producing a first output signal whenever an input di function signal contains two consecutive high voltage levels and a second output signal whenever the di-function signal contains two consecutive low voltage levels.

A further object of the present invention is to providr a device for delaying a di-function signal for one tim ing interval and for producing first and second output signals whenever the di-function signal and the delayed di-function signal are simultaneously at their +1 and 1 values, respectively.

Other objects and features of the present invention Will be readily apparent to those skilled in the art from the following specification and appended drawings wherein is illustrated a preferred form of the invention, and in which:

Fig. 1 is a block schematic diagram of the computer and indicator system according to the present invention; Fig. 2 is a block schematic diagram of an electrical circuit employed to illustrate the principles involved in illustrating the devices of the present invention;

Fig. 3 is a detailed circuit diagram of the block schematic diagram of Fig. 2;

Fig. 4 is a composite group of signal waveforms representing the operation of the circuit of Fig. 3;

Fig. 5 is a block schematic diagram of a bi-directional di-function quantizer according to the present invention;

Fig. 6 is a block diagram illustrating the programming of the quantizer according to Fig. 5;

Figs. 7a and 7b are a pair of block schematic diagrams of two forms of di-function half-adder circuits according to the present invention;

Fig. 8 is a block schematic diagram of the deconverter according to the present invention;

Fig. 9 is a composite group of signal Waveforms illustrating the principle of operation of the deconverter of Fig. 8;

Fig. 10 is a composite group of signal waveforms illustrating the principles of operation of the computer and indicator system of Fig. l; and

Fig. 11 is a block schematic diagram of a uni-direc tional di-function quantizer according to the present invention.

Referring now to the drawings wherein identical elements are given the same numerical designation, there is illustrated in Fig. 1, the computer and indicator system according to the present invention for producing a binary number count representing the angular displacement between two rotating shafts. The first rotating shaft 20, formed of electrically conductive material, has a disc 22 aifixed thereto. Disc 22 is also formed of electrically conductive material with the exception of a non-conducting or insulated ring or segment 23 extending around a major portion of the periphery thereof. A commutator segment 24 is formed between the ends of insulated segment 23 and provides a narrow conductive arm or commutator segment extending to and lying along the periphery of the disc.

A spring loop 26, in conductive contact with shaft 20, is connected to the positive terminal of a source of potential, such as battery 27, the negative terminal of battery 27 being connected to ground. Disc 22 is contacted .at its periphery by three brushes A, B and C which are,

in turn, conductively coupled to three of the input terminals, respectively, of a first di-function quantizer 34. A detailed description of the circuitry and mode of operation of quantizer 34 will later be presented in connection with Figures 5 and 6 of this disclosure.

The second rotating shaft 36 has a disc'37 affixed thereto, disc 37 being similar in all respects to disc 22. Shaft 36 is also contacted by a spring loop 39, similar to loop 26, loop 39 being also connected to the positive terminal of battery 27. The periphery of disc 37 is contacted by three parallel brushes, L, M and N, similar to brushes A, B and C, respectively, which are connected to three of the input terminals of a di-function quantizer 42, similar to quantizer 34.

The output terminal of a source 44 of timing signals, lesignated cl, is connected to a final input terminal of each of quantizers 34 and 42 while the pair of complementary output signals, designated p and p, of quantizer 34 are applied to two of the input terminals of a di-function serial half-adder or averager 45. The pair of complementary output signals, designated q and q, of quantizer 42 are applied to two additional input terminals of adder 45 while the timing signal of source 44 is applied to a final input terminal of adder 45.

Timing signal source 44 produces a repetitive output signal waveform of alternate low and high voltage levels, and may, for example, comprise any conventional square wave generator or multivibrator circuit. A detailed description of the circuitry and operation of half-adder 45 will be later presented in connection with Fig. 7 of this disclosure. 7

The pair of complementary output signals, designated a and e, of adder 45 are applied to two of the input terminals of a di-function deconverter 46 while timing signal cl is applied to a third input terminal thereof. A detailed description of the circuitry and mode of operation of deconverter 46 is later found in connection with Figures 8 and 9 of this disclosure.

The two output conductors 47 and 48 of deconverter 46 are connected through differentiating circuits 47a and 480, respectively, to the two input terminals of an updown counter 49. Counter 49 may be of any conventional binary type having two input conductors which increases its count one binary digit in response to a signal applied to one input conductor and decreases its count one binary digit in response to a signal applied to its other input conductor. Such a counter is illustrated and described in an article entitled A Binary Quantizer" by Kay Barney, appearing on pages 963 and 964 of the No vember 1949 issue of the magazine Electrical Engineer ing. The particular counter therein disclosed increases and decreases its count in response to positive and negative pulses, respectively.

In order that the system of Fig. 1 may operate properly, certain relationships should exist between various physical and electrical parameters thereof. First of all, the frequency of the timing signal cl must be sufficiently high relative to the maximum angular velocity attained by shafts 20 and 36 such that two timing intervals will be generated during any given contact between their respective commutator segment and any one of their respective brushes.

Also, the thickness of any of the brushes, A, B or C should be so related to the width of segment 24, as meas ured along the periphery of disc 22, that only one brush will contact segment 24 at any given instant.

A detailed account of the operation of the entire system of Fig. 1 will be set forth in connection with Fig. 10 after the circuitry'and principles of operation of quantizers 34 and 42, adder 45, and deconverter 46, here indicated only in block diagrammatic form, have been presented. In brief, it may be stated that each of quantizers 3 4 and 42 produces a pair of complementary output signals in average form, the di-function values of which indicate, for any given interval of time, both the magnitude and direction of the angular velocity, with respect to a predetermined maximum velocity, of its associated shaft. The counter-clockwise direction of rotation of shafts 20 and 36, it should be here noted, is taken to be positive with the clockwise direction of rotation being taken as nega tive.

Adder 45 then adds the di-function output signal of quantizer 34 to the inverted or complementary di-function output signal of quantizer 42 to produce an output difunction signal whose average value represents the difference in average values between the two output signals from quantizers 34 and 42. Stated differently, adder 45, owing to the manner in which the input signals from quantizers 34 and 42 are applied thereto, produces an output di-function signal the average value of which represents the subtracted result of the di-function output si nal of quantizer 42 from the di-function output signal of quantizer 34.

The average value of the di-function output signal from adder 45, taken over a given interval of time, in turn, indicates the magnitude of the difference in angular displacement between shafts 29 and 36 for this interval of time and the sign of this value indicates the direction of this relative displacement.

' Deconverter 46 changes the information contained in the di-function output signal of adder 45 into information in a voltage level or pulse type of form as it appears on its output conductors 47 and 48. In particular, if the output signal of adder 45 has an average value of zero, as represented by a series of alternate +1 and -1 instantaneous 'di-function values, then deconverter 46 does not produce an output signal on either of its output conductors. However, if an extra +1 instantaneous di-function value is contained in the adder ouput signal, then deconver-ter 46 produces a high output voltage level lasting for one timing interval on conductor 4'7. If, on the other hand, the adder output signal contains an extra 1 value, then deconverter 46 produces a high output voltage level lasting for one timing interval on conductor 48.

Differentiating circuit 47a differentiates the leading and trailing edges of all output voltage levels appearing on conductor 47 into positive and negative pulses, respectively, the positive pulses being effective to operate counter 49, as described in the before referred to article, into increasing its count one binary digit value. Diiferentiating circuit 48a, likewise produces positive and negative pulses for each voltage level appearing on conductor 48, each negative pulse thereof being effective to operate counter 49 into decreasing its binary count by one binary digit value.

If the binary number count of counter 49 is positive, it indicates that shaft 2t) has made an overall counterclockwise displacement relative to shaft 36 during the period of the count. If the count is negative, it indicates an overall clockwise displacement of shaft relative to shaft 36. If, during a short period of time, the count is increasing, it indicates that the rotation of shaft 20 relative to shaft 36 during that period is in a positive or counter-clockwise direction. If this count is decreasing, it indicates that the rotation of shaft 20 relative to shaft 36 during that period is in a negative or clockwise direction.

'Quantizers 34 and 42, adder and deconverter 46 each comprise intricate combinations of and gating circuits, or gating circuits, and flip-flops, each combination being an electrical realization or mechanization of a mathematical equation in Boolean form. Since the basic principles involved in mechanizing all Boolean expressions are identical, the mechanization of a pair of simple equations is illustrated in Figures 2 and 3 so that the principles involved in this example, once understood may be readily applied to more complex equations of the type defining the quantizers, adders and deconverter.

The mechanization illustrated in Figures 2 and 3 is of the two Boolean equations:

In particular, in Fig. 2, there is illustrated the mechanization of Equations 1 and 2 into a schematic representation in which each of the and and or gating circuits and the flip-flop is set forth as an individual block. Thus, in Fig. 2, timing signal source 44- produces a timing or clocking signal, designated cl, on its output conductor. A flip-flop B produces on its two output conductors, two complementary output signals, b and b, respectively, while a fiip-fiop C produces complementary output signals c and c on its two output conductors, respectively. Also, a flip-flop D produces complementary output signals d and a" on its two output conductors, respectively. Each of the pairs of complementary signals, 1) and b, .c and c, and d and d comprise complementary alternate high and low voltage levels, each of the voltage levels appearing for an integral number of timing intervals as clocked by signal cZ.

Flip-flop A includes a pair of input conductors, designated S, and Z,,, respectively, and produces two complementary output signals a and a on its two output conductors, respectively. The 8,, or Set a, input conductor of flip-flop 'A denotes that flip-flop A will be triggered into its set state by any signal applied thereto such that output signal a will be at its high voltage level. Since, by definition, the high voltage level is equal to an instantaneous di-function value of +1; a signal applied to the S input terminal will trigger flipfiop A so that signal a will equal +1. When this is done, complementary signal a will be at its low voltage level and hence, equal to an instantaneous di-function value of -1.

The Z,,, or Zero a, input conductor denotes that flipflop A will be triggered by any signal applied thereto into its zeroed state in which signal a is at its low voltage level and hence, equal to an instantaneous difunction value of 1. When this is done, signal a will be at its high voltage level and hence, equal to an instantaneous di-function value of +1.

As will be brought forth later in connection with Fig. 3, fiip-flop A is of the bistable type having two stable states. Thus, once the value of signal a is made equal to +1 by a signal applied to conductor S it will remain at that value until another signal is applied to Z input conductor at which time it will change to the -1 value.

Equation 1, for 8,, denotes that an input pulse is to be applied to the S input conductor each instance signals cl and b are simultaneously at their high voltage level. Stated differently, Equation 1 defines that signal S is high whenever signal b is high and signal cl is high. As is well understood by those skilled in the computer art, the logical operation defined by this Boolean equation may be readily mechanized by a well-known and gating circuit which receives the input signals b and cl and produces the output 8,. In particular the logical operation defined by Equation 1 is accomplished by connecting the two input terminals of a two terminal and gating circuit 52 to the output conductor of source 44 and the [7 signal output conductor of flip-flop B, respectively. The output conductor of circuit 52, on which appears the logical product b-cl signal, is connected to input conductor 8,. And gating circuit 52 is illustrated by a block having X therein, the X representing that its output signal is the logical product or and function of the input signals applied thereto.

Equation 2 for Z denotes that an input signal is to be applied to the Z input conductor to make a=1 each instance either of signals c or d is at its high voltage level at the identical time signal cl is at its high voltage level. Stated difi'erently, Equation 2 defines that signal Z is high whenever signal c is high or signal d is high and signal cl is high. As is well understood by those skilled in the art, this equation defines two logical operations, namely an or operation as defined by the sign and an and operation as defined by the sign, which can readily be mechanized by well-known or and and gating circuits, respectively. In particular, the equation is mechanized by connecting the c and d signal output conductors of flip-flops C and D, respectively, to the two input terminals of a two terminal or gating circuit 54, respectively, and then con-- necting the output conductor of circuit 54 and signal source 44 to the two input terminals, respectively, of a two terminal and gating circuit 56, similar to circuit 52. The output conductor of circuit 56 is, in turn, connected to input conductor Z,,. Or gating circuit 54 is illustrated by a block having a sign therein, the representing that its output signal is the logical sum or or function of the input signals applied thereto.

In order that the exact operation of the circuit of Fig. 2 may be understood, a detailed structural embodiment thereof is set forth in Fig. 3. This detailed embodiment is intended to illustrate the basic operational principles involved upon the application of input signals to and and or gating circuits, and their resulting operations. in connection with a flip-flop. With these principles established, the operation of the more complex circuits as set forth later in block diagram form of the quantizer, adder, etc., may be readily understood.

In particular, the output conductor of source 44 is connected to the cathode of a diode 60 within and gating circuit 52 while the b signal output conductor of flip-flop B is connected to the cathode of a diode 61 also within circuit 52. The anodes of diode 60 and 61 are connected together at a common junction 62, junction 62 being connected to the positive terminal E of a source of potential (not shown) through a resistor 63. Junetion 62 is, in turn, connected to the 5,, input conductor of flip-flop A.

The c signal output conductor of flip-flop C is connected to the anode of a diode 67 within o'r" gating circuit 54 while the d signal output conductor of hip flop D is connected to the anode of a diode 68 also within circuit 54. The cathodes of diodes 67 and 68 are connected together at a common junction 70, junction 70 being connected through a resistor 72 to the negative terminal E of a source of potential (not shown).

Common junction 70 is connected to the cathode of a diode 73 within and gating circuit 56 while the output conductor of source 44 is connected to the cathode of a diode 74 also within circuit 56. The anodes of diodes 73 and 74 are connected to a common junction 75, junction 75 being connected through a resistor 76 to terminal E Common junction 75 is, in turn, connected to the Z input'conductor of flip-flop A.

Considering now the circuitry of flip-flop A, the S input conductor thereof is connected to one plate of a capacitor 78, the other plate of capacitor 78 being connected to the cathode of a diode 79. The anode of diode 79 is connected 'to the grid of a first triode 80. The Z,, input conductor is connected serially through a capacitor 82 and a diode 83 to the grid of a second triode 84. The cathodes of diodes 79 and 83 are connected through a pair of resistors indicated at 81 to the positive terminal E of a source of potential (not shown).

The cathodes of triodes 80 and 84 are connected to ground while their grids are connected through respective grid resistors to negative terminal E The anode of triode 84 is connected through a paralleled resistorcapacitor combination 88 to the grid of triode 80 while the anode of triode 80 is connected through a paralleled resistor-capacitor combination 89 to the grid of triode 84.

The anodes of triodes 80 and 84 are connected through plate resistors 90 and 91, respectively, to terminal E The anode of triode 80 is also connected to the cathode of a clamping diode 92, the anode of diode 92 being connected to the positive terminal E of another source of potential (not shown). The cathode of another clamping diode 93 is connected to the anode of triode 84, the anode of diode 93 being connected to terminal E The anode of still another clamping diode 94 is connected to the anode of triode 80, its cathode being connected to 'the positive terminal E of still another source of potential (not shown). The cathode of yet another clamping diode 95 is connected to terminal E its anode being connected to the anode of triode 84.

The magnitude of the potential appearing on the ter rninals E E E E and E may, for example, have the values of +250 v., 250 v., +100 v., +140 v., and +5 v., respectively. As is apparent, the small .positive potential from terminal E is applied to bias the cathodes of diodes 79 and 83. The a signal output conductor of flip-flop A is connected to the anode of triode 80, while the a signal output conductor is connected to the anode of triode 84.

The operation of the circuitry of Fig. 3 may be most readily understood by reference to the composite diagram of signal waveforms appearing at various points in the circuit of Fig. 3 as are illustrated in Fig. 4. The output signal, generally designated 100 in Fig. 4, of'timing signal source 44, comprises a series of alternate low and high :voltage :levels, defining a series of designated 12 timing intervals. As indicated, the voltages of the high and low voltage levels of signal are equal to the voltages appearing on terminals E and E respectively. Also, the high and low levels are illustrated as being substantially equal in duration. However, as will be later recognized, other similar types of waveforms may be utilized for clocking purposes, for example, those produced by blocking oscillators.

The signal, generally designated 102 in Fig. 4, is output signal b and is, for the purposes of this example, at its high voltage level during the first and sixth timing intervals, and at its low voltage level during the remaining timing intervals. The signal, generally designated 108 in Fig. 4, is output signal 0 and is, for this example, at its high voltage level during the third and fourth timing intervals while the signal, generally designated 110 in Fig. 4, is output signal d and is at its high voltage level during the fourth and seventh timing intervals. The high and low voltage levels of each of signals 102, 108 and 110 are equal to the voltages appearing on terrninals E, and E respectively.

During the first half of the first timing interval, timing signal 100 is at its low voltage level, while signal 102 is at its high voltage level. Thus, the potential of the signal, generally designated 104 in Fig. 4, appearing on common junction 62 of and gating circuit 52 is at the low voltage level E owing to the direction of connection of diodes 60 and 61. During the second half of this first timing interval, signal 100 switches to its high voltage level, and signal 104 rises exponentially to the high voltage level B, by reason of capacitor 78, within flip-flop A, being slowly charged from terminal E through the relatively high resistance of resistor 63. The values of capacitor 78 and resistor 63 should be so related as to have the charging of capacitor 78 substantially completed by the end of this timing interval.

At the beginning of the second timing interval, signal 100 switches to its low voltage level E with the result that capacitor 78 is discharged to that voltage level, the discharge taking place through its associated resistor 81, whose value is relatively low in comparison with the resistance of resistor 63, hence allowing a relatively quick discharge of capacitor 78 therethrough. This quick discharge through resistor 81, in turn, produces a sharp negative pulse thereacross, which negative pulse, after conduction through diode 79, appears on the grid of triode 80. The signal, generally designated 106 in Fig. 4, appearing on the grid of triode 80 illustrates this pulse as it appears at the beginning of the second timing interval.

It is assumed that, for the first timing interval, triode 80 was fully conducting and hence, output signal a, generally designated 118 in Fig. 4, was at its low voltage level. The pulse in signal 106, appearing at the beginning of the second timing interval, lowers the potential on the grid of triode 80 such that triode 80 becomes non-conducting with a corresponding rise of its anode potential. This rise is, in turn, coupled to the grid of triode 84 through resistor-capacitance combination 89 so that triode 84 begins conduction. This, in turn, results in signal a, generally designated 120 in Fig. 4, appearing on the anode of triode 84 changing from its high voltage level of the first timing interval to its low voltage level during the second timing interval.

In considering the action of the clamping diodes "92 and 94, it should first be stated that the particular relationship existing between the potential appearing on terminal E the resistance of resistor 90 and the tube characteristic of triode 80 are such that the normal high and low voltage levels appearing on the anode of triode 80 are greater and less than, respectively, the potentials appearing on terminals E and E respectively. Thus, with triode 80 non-conducting, its high voltage level will be lowered to the potential appearing on terminal E owing to the shunting action of diode 94. On the other hand, with triode 80 conducting, its low voltage level will be raised to the potential appearing on terminal E owing, in this case, to the shunting action of diode 92. Since this same effect is applied to the high and low voltage levels appearing on the anode of triode 84 by diodes 95 and 93, respectively, it is seen that the complementary signals a and a will always be at either the E and E potentials, respectively, or at the E and E potentials, respectively.

Summarizing the circuit operation thus far presented, it is seen that when the voltage levels appearing on the two input conductors to and gating circuit 52 are both high during a timing interval, the signal applied thereby to the 8,, input conductor produces a change in the con duction state of flip-flop A such that signal a changes from its low to high voltage level, or expressed in difunction terms, changes from a 1 to a +1 value during the next timing interval. As is readily apparent, any additional negative pulses applied to the grid of triode 80 from circuit 52 and capacitor 78 will have no effect on the conduction state of flip-flop A, owing to the cutoff condition of triode 80.

Signal 108 is at its high voltage level during the third timing interval, with the result that the signal, generally designated 112 in Fig. 4, appearing on common junction 70 of or gating circuit 54, will, owing to the direction of connection of diodes 67 and 68, be likewise at the high voltage level. Signal 112 is applied to and gating circuit 56 along with signal 100 with the result that the potential of the signal, generally designated 114 in Fig. 4, appearing on junction 75 of circuit 56 will rise exponentially to the high voltage level E during the last half of this third timing interval. This potential rise is due to the charging up of capacitor 82 of flipflop A from the E terminal through resistor 76.

Upon signal 100 switching to its low voltage level at the beginning of the fourth timing interval, capacitor 82 discharges rapidly through its associated resistor 81, terminal E to ground, with the result that a negative pulse is produced across this resistor 81 at the beginning of the fourth timing interval. This pulse, after conduction through diode 83 appears in the signal, generally designated 116 in Fig. 4, applied to the grid of the then-conducting triode 84. Triode 84 is rendered non-conducting thereby with its resulting anode potential rise being coupled through resistor-capacitor combination 88 to the grid of triode 80 to thereby cause triode 80 to begin conduction. Thus, signals 118 and 120 switch to the low and high voltage levels, respectively, at the begining of the fourth timing interval to indicate, in di-function terms a=1 and a'=+1. It is thus seen that when either of signals 0 or d is at its high voltage level, gating circuit 54 applies a high voltage level to gating circuit 56 which, in conjunction with timing signal cl, triggers flip-flop A through its Z input conductor.

The remaining portions of the signal waveforms, illustrated in Fig. 4 may be readily understood from the description set forth above. It should be noted that or gating circuit 54 produces a high voltage level in signal 112 when either or both of the input signals applied thereto are at their high voltage level. This is due to the direction of connection of diodes 67 and 68 and the fact that the potential appearing at terminal E is of negative polarity.

From the description of operation thus far presented for the circuit of Fig. 3, it is apparent that and gating circuits 52 and 56 and or gating circuit 54 may be extended to include additional input conductors. Thus, any additional input conductors to circuit 52 would be coupled through diodes, similar to diodes 60 and 61, to common junction 62. With this done, the gating circuit would produce a pulse at the triode 80 grid of flip-flop A only when each of its input conductors had a high voltage level applied thereto.

In the same manner, any additional input conductors 14 to or gating circuit 54 would be coupled to common junction 70 through diodes similar to diodes 67 and 68, and the resulting circuit would produce a high output voltage level when a corresponding voltage level appeared on any given one of its input conductors.

It should be apparent, therefore, that Boolean equa tions defining various combinations of logical and and or functions may be readily mechanized by the wellknown and and or gating circuits, respectively. More particularly, each logical and function set forth in a Boolean equation by means of a sign will be mechanized by an and gating circuit having a number of input terminals equal to the number of factors included by the sign, while each logical or function set forth by means of a sign will be mechanized by an or gating circuit having a number of input terminals equal to the number of terms included by the sign. Although each or sign may be considered to represent a separate logical function mechanizable by a separate gating circuit, it is preferable, for purposes of circuit simplicity, to mechanize consecutive like signs by a single gating circuit having one input terminal and one diode for each term or factor included by the consecutive like signs. For example, the logical and operations a.b.c.d would be mechanized by a four-terminal and gating circuit, while the logical or operation a+b+c would be mechanized by a three-terminal or gating circuit.

In the detailed description of Fig. 1 which follows, each of the circuits will be considered first from the standpoint of its overall function, then from the Boolean equations which define this overall function, and finally a specific mechanization of these equations. The mechanization described will be based upon the general principles of and and or circuits set forth above.

The first circuit of Fig. l to be illustrated and described in detail is that of quantizer 34. The function performed by quantizer 34 is that of converting the angular rotation of shaft 28* into an output signal in average form, the difunction value of which, considered over an interval of time, represents the magnitude of the angular displacement during that time interval with the sign of the difunction value representing the direction of the shaft displacement, that is, whether the displacement was in a positive or negative direction. The circuitry of quantizer 34 is set forth in detail in Fig. 5 while a so-called programming diagram is set forth in Fig. 6, the programming diagram illustrating one of the means followed in deriving the specific circuitry of Fig. 5.

The broad principles of operation of quantizer 34 will be first set forth before preceding with the description of the derivation of the specific circuitry thereof. In the first place, a principal electronic switch, such as flip-flop P, is employed whose pair of complementary output signals p and p comprise the quantizers output di-function signals. Appropriate diode gating circuitry and programming flip-flops are provided within the quantizer to normally trigger flip-flop P into changing its conduction state at the beginning of each timing interval with the result that signal p normally contains a series of alternate +1 and 1 di-function values representing an average difunction value of zero.

However, this triggering circuitry is rendered inoperative to trigger flip-flop P into producing its next regularly occurring low voltage level or 1 value in signal p upon each complete revolution of shaft 20 in its designated positive or counterclockwise direction. Also, the triggering circuit is rendered inoperative to trigger flip-flop P into producing its next regularly occurring high voltage level or +1 value in signal p upon each complete revolution of shaft 20 in its negative or clockwise direction. This results in the production of two consecutive high voltage levels or +1 values for each revolution of shaft 20 in the positive direction and in two consecutive low 15 voltage levels or 1 values for each revolution of shaft 2% in the negative direction.

In order to provide the necessary triggering sequences for fliphop P, two programming or memory electronic switches, such as flip-flops I and J, are utilized, flip-flop I producing two complementary output signals i and i and flip-flop I producing two complementary output signals j and j.

Programming flip-flops I and I are required since a relatively large number of contact sequences is possible between segment 24 and brushes A, B and C upon various magnitudes of positive and negative angular displacements of shaft 2! For example, segment 24 may sequentially make the following brush contacts; B to A to B, B to A to C, B to C to B, B to C to A, etc. In quantizcr 34-, the brush contact sequence B to A to C is defined as one complete revolution of shaft 2t) in the positive direction while the contact sequence B to C to A is defined as one complete revolution of shaft 20 in the negative direction.

As will be apparent, a wide variety of partial sequences may occur before a complete positive or negative sequence as above defined is concluded. Flip-flops I and I serve as memory devices in that the different contact sequences produce different triggering sequences thereof such that their conduction states, at any given instant, indicate the particular contact sequence just completed. Thus, their conduction states produced by the above defined positive and negative shaft rotations are utilized to provide appropriate triggering for flip-flop P so that signal p will have the above stated characteristics.

The programming diagram of Fig. 6 serves to indicate in a schematic manner, the particular triggerings of flipfiops P, I and J upon all possible sequences of contact between segment 24 and brushes A, B and C. As will be apparent, although all of such possible contact sequences must be considered, the particular triggerings of flip-flops P, I and I produced by any given sequence was arbitrarily chosen as the first step in the design process.

A Programming Table I is herewith included below to be considered concurrently with Fig. 6, Table I additionally serving later as a basis for writing the Boolean equations defining the gating circuitry found in Fig. 5.

Programming Table I 16 Similarly, the potential at brushes A, B and C when the brushes are not contacting segment 24 should be equal to the low voltage level appearing on terminal E in Fig. 3, so that signals a, b and 0 will be incapable of opening any gating circuits when the brush is not in contact with segment 24. This result may be readily accomplished by connecting terminal E to brushes A, B and C through suitable resistors.

The Idle program, as defined and illustrated in the lefthand block as viewed from Fig. 6, exists whenever segment 24, after having contacted brush B, presently lies between brushes A and C. During this program, flip-flop P is to be alternately triggered so that p equals +1 and 1 during successive timing intervals while flip-flops I and J are triggered to produce a steady i=l and j=l. This program is likewise indicated on line 1 of Table I.

From the Idle program position, segment 24 may travel and contact either brush A or brush C. If brush A is contacted, the Alpha (a) program, as indicated in the upper block, as viewed from Fig. 6, is to be generated or set into the flip-flops at the beginning of the next timing interval. Program Alpha, as will be noted, contains both p=il and p=1 denoting that flip-flop P is alternately triggered as it was during the Idle program while flip-flop J is triggered, as indicated in column 9, line 2 of Table I, to produce j=+l, flip-flop I remaining unchanged to produce i:1.

After contacting brush A, segment 24 may contact either brush B again or may contact brush C. If brush B is contacted, then program Idle must be again generated as indicated on line 3, by triggering flip-flop J, at the beginning of the time interval following this new contact with brush B, to produce j==-1.

If, during the Alpha program, segment 24 contacts brush C, then, by definition, one complete revolution of shaft 20 has been made in the positive direction, and to indicate this revolution, as has been stated, flip-flop P is to produce p=+l for two consecutive timing intervals. This is accomplished by generating a Gamma (7) program, as indicated in the right hand block as viewed from Fig. 6, the Gamma program being a transitory one lasting for only one timing interval. This Gamma program is, at the end of this one interval, automatically Brush Contents Line To Generate Con-c: spends in program- Output ming +1 1 diagram Idle (I) In Table I, columns I, 2 and 3 are devoted to the signals a, b and c appearing on brushes A, B, and C, respectively, owing to possible contacts made between them and segment Upon such a contact, the potential of potential source 27 is applied to the brush contacted with the brusus corresponding signal having a di-function value of +1. As will be apparent, the potential of battery 27 should equal the high voltage level appearing on terminal E in Figure 3 so that it will be capable of opening any gating circuits to which it may be applied.

programmed by the timing signal into a stable Beta (,3) program as indicated by the lower block in Fig. 6.

This transition from the Alpha program to the Beta program through the intermediate Gamma program is begun only during the timing interval that segment 24 contacts brush C while signal p=-1. This is possible since, by previous definition, the timing signal frequency must be so related to the maximum shaft rotational speed as to produce two timing intervals during any single contact between commutator segment 24 and any given one h'and' portion of the Beta program block. n'ient 24 should contact brush B, the Idle program will againbe generated during the timing interval of this con- 'tact that p=+1 by triggering flip-flop I to produce val bytriggering flip-flop I to produce i=1.-

-:of:the br'ushesq' Thus, brush C, ifcontacted durin'g 'the *Alpha program; will be contacted during two consecutive timing intervals and signal p will accordingly have the values of either +1 and +1 or +1 and +1 during these two intervals.

I If this contact. should be made when p=.+'1, then the .hbld Alpha program as indicated on line .4 of Table I .was set equal to +1 at the beginning thereof. Now, at -the 'beginningof the next timing interval, program .Gam-

rna' 'isto be automatically generated into program Beta with flip-flop P producing an extra p=+1 .to indicate thereby, one complete positive shaft revolution. Thus, on

line 6, column .7, fiip-flopP is tocontinue producing p:+1 during this next timing interval while j=+1 is to be generated as indicated'in column 9. With this accomplished,.program Beta initially begins with 'p=+1 ,'i="-]-1 Once program Beta has again vary between +1 and +1 during consecutive timing intervals while signals i and j will remain equal to +1 and +1, respectively, as indicated in the left hand I If now, segi:+1 as indicated on line 8 of Table I. V

If segment 24 should contact brush C during the Idle program, as indicated on line 10, the Beta program will be'generated at the beginning of the next timing inter- If shaft 20 continuesto move in this negative direction of rotation until segment 24 contacts brush A then, by definition, shaft 20 has made one complete revolution in the negative direction and the transitory Gamma program is generated from the Beta program. i

' During the first instant of contact between segment 24 and brush A, signal p may be equal to +1 or +1. If p is equal to +1, line 11 of Table I is observed and none of the flip-flops are triggered thus holding the Beta program for that interval. During the next timing interval, as indicated on line 12, p=+1 and to generate the Gamma program, flip-flop I must be triggered to produce j=+1. With-this accomplished, as indicated on line 13,

p=+1, and i and j both equal to +1.

The Alpha program is then automatically generated at the begining of the next timing interval from the transitory Gamma program such that flip-flop P produces an extra p=+1 to indicate one complete revolution of shaft 20 in a negative direction. Also, flip-flop I must be triggered to produce i=1, these triggerings of flip-flop P and I being indicated in columns 7 and 8, respectively, of line 13. The Alpha program, as indicated on line 14, is thus generated at the beginning of the next timing interval. With no further rotation of shaft 20, program Alpha is maintained with signal p once again varying between +1 and +1 during successive timing intervals and with signals i and 1' being equal to +1 and +1, respectively.

As isapparent, if commutator segment 24 should have first contacted brush A in the example just given during a timing interval when p=+1, the hold Beta program indicated on line 11 would be unnecessary and the Beta to Gamma program indicated on line 12. would have been immediately generated during the next timing interval.

If segment 24 contacts brush B after contacting brush C, the Idle program, as again illustrated on line 16, will be generated during the timing interval of the contact when p=+-1, as indicated on line 15,

been generated,signal p will' found in Table I may be readily written and from them a circuit mechanization obtained capable of electronically .producingeach program upon completion of its corresponding brush contact sequence. For example, in writing theBoolean equations representing the circuitry to be connected to the 8, input conductor of flip-flop I, it is apparent by inspection of the to generate column 8 of Table I triggering signals are to be applied to this ,conductor only during those timing intervals found on lines 5 and 10 where the +1 symbols appear. The +1 symbol, as will be remembered, appears whenever flipflop I is to be triggered at the beginning of the next following timing interval to produce i=+1 at that time. Thus,.for line 5- of Table I, it is seen that flip-flop I is to be triggered to produce i= +1 whenever signals 1; iand j are simultaneously equal to +1, +1 and +1, respectively, with brush C being contacted by segment 24 so that 0:1. This signifies electronically that an and gating circuit should be employed capable of producing a. triggering signal at the S conductor upon each occurrence of this particular combination of p, i, j and c signals. However, the p and i signals cannot be used directly'as gating signals since they are at their +1 or low.voltage level and hence, incapable of opening an :and gating circuit of the type illustrated in Fig. 4. (Therefore, the complementary signals p and i must be used since they will be at their high voltage level or +1 value whenever signals p and i are equal to +1.

,Accordingly, bearing in mind the timing signal cl, the Boolean expression for line 5 will be:

of the and gating circuit. The expression when p=-+1 will be:

S =c'p-i-j'-cl (Eq. 4)

and the expression when p=1 will be:

S =c-p'-i'-j'-cl (Eq. 5)

Equation 6 may be readily mechanized by employing the principles outlined in connection with Fig. 2. However such a mechanization will not result in the simplest circuit embodiment, that is, one having the fewest possible number of gating circuits and yet still be capable of producing the desired result. However, by employing various so called logical or Boolean tautologies, Equation 6 may be simplified to a minimum number of terms which, in turn, when mechanized, yield the simplest circuit embodiment. This reduction results in:

I FUH-P') q- As will be understood by those skilled in the art, each equation derived in the process of simplifying Equation 6, or for that matter, each and every equation which may be written from Equation 6, whether expanded or reduced, represents a circuit embodiment capable of performing the electrical results desired for the circuit mechanization of Equation 7. Obviously, the scope of illYfiHIiQll is intended to include the mechanization of all such possible equations although only one such circuit is illustrated. The same holds true for each of the In the same manner the equation for 8 may be written from Table I as:

Also, the equation for Z may be written from Table I and simplified to:

The equations for S and Z may be derived in several ways including the way set forth above for the S Z etc. equations. However, the most readily understandable technique is to bear in mind that flip-flop P is to be alternately triggered by signals applied to its S and Z input conductors except when the conditions appearing on lines 6 and 13 of Table I are present, that is, when both i and j are equal to +1. This, in turn, leads by inspection to the equations:

In equation 13, for example, if i and j are both equal to +1, then their corresponding complementary signals i and j are both equal to 1, and the or gating circuit, representing the portion of the equation (i'+j) will produce a low output voltage level which will be incapable of opening the and gating circuit connected to the S input conductor. Since the same is also true for Equation 14, it is seen that Equations 13 and 14 satisfy the specified triggering requirements for flipflop P.

Referring now again to Fig. 5, there is illustrated quantizer 34 embodying the electrical mechanization of Boolean Equations 7, 9, ll, 12, 13 and 14. The mechanization of each equation is performed in the manner set forth previously in the example of Figures 2 and 3, and no repetition of the steps followed is deemed necessary. In order to render the circuit diagram more readily understandable, the A, B and C brushes, the p, p, z', i, j and j signal output conductors, and the output conductor of source 42 are each connected to a corresponding vertical bus, as viewed from Fig. 5, each bus being designated in accordance with the signal applied thereto. The input terminals of each gating circuit are, in turn, connected to the appropriate vertical buses as defined in its corresponding Boolean equation.

It will be noted that a common term (i -l-j') appears in Equations 13 and 14, defining S and Z respectively. In mechanizing these equations, only one or gating circuit, namely, gating circuit 100 of Fig. 5, is employed, its two input terminals being connected to the i and j buses, respectively. Its output terminal is connected to two and gating circuits 102 and 104 which form the remaining portions of Equations 13 and 14, respectively.

It is, therefore, seen that Equation 13, which includes one sign and two signs is mechanized by means of one an gating circuit and one or gating circuit. More particularly, the sign is mechanized by means of twoterminal or gating circuit 100 receiving signals 1" and j',

and the two signs are mechanized by a single threeterminal and gating circuit, namely circuit .102, receiving signals p, cl and the output signal of circuit 100. Similarly, Equation 14, which also contains one sign and two signs, is mechanized by or gating circuit and three-terminal and gating circuit 104which differs from circuit 102 only in the receipt of signal .p rather than p.

Equation 7 contains one sign and three signs and is mechanized in Fig. 5 by means of one two-terminal or circuit and one four-terminal and circuit, respectively. Equation 9, on the other hand, contains a single sign defining an or operation on complex and terms (b-j') and (p-j), and two additional signs. The two complex and terms of the or operation are mechanized by two-terminal and gating circuits, the or operation by one two-terminal or gating circuit, and the remaining two signs by a three-terminal and gating circuit.

Equation 11 includes a sign andthree signs which are mechanized in Fig. 5 by a two-terminal or gating circuit and a four-terminal and gating circuit, respectively. Equation 12, on the other hand, is similar to Equation 9 and has the same gating circuit arrangement except for the interchange of signals i and j.

At this point it is helpful to trace through one of the sequences shown in Table I and Fig. 6 in order to establish the operability of the mechanization of Fig. 5. Assume first that the quantizer of Fig. 5 is in its idle condition, that is with signals 1' and j equal to 1, and that segment 24 lies between brushes A and B. Under these conditions, the output signal from or gating circuit 100 will be high (i=j'=+1) and the state of flip-flop P will be changed every timing interval by means of and circuits 102 and 104. On the other hand, since brushes C and A are at their relatively low level potentials the S and S and gating circuits cannot be opened and signals 1 and j will remain at 1, as shown in line 1 of the table.

If brush A is now contacted by segment 24, as shown in line 2 of Table I, then all of the conditions for the S and gating circuit are satisfied, and flip-flop I is triggered to set signal j to +1 and thereby initiate the a program shown in Fig. 6 and line 2 of the table. Since signal i still remains at l, the output of or gating circuit 100 will remain high and flip-flop P will still be changed every timing interval.

During the passage of segment 24 in the counter-clockwise or direction from brush A to brush C, signal i remains l and, therefore, signal p alternates in level each timing interval. At the same time, since signal b also remains 1, Equation 12 for 2; cannot be satisfied and signal j remains at +1. Therefore, the a program is maintained until segment 24 contacts brush C.

When segment 24 contacts brush C, signal p may be either +1 or 1 as indicated in lines 4 and 5 of Table I. If signal is +1, then the output of the or gating circuit in the S input of Fig. 5 remains low (since p=j=1) and signal 1' remains at 1. At the same time signal j remains +1 and the or program is held as indicated in line 4 of the table. On the other hand, when signal p is 1, the output of the or gating circuit becomes high and signal i becomes +1. Since signal j remains +1, the a program is transformed to the 7 program, as shown in Fig. 6 and line 5 of the table.

At this point signal i and j are both +1. Similarly, signal p is +1 since it was just changed from --1 at the same time that signal i was changed. Under these conditions, the output signal from or gating circuit 100 will be at its low level (i=j=-l), and no signal will be applied to flip-flop P. Accordingly, signal p will remain +1 for a second consecutive timing interval, as indicated by line 6 of Table I. At the same time, since signals p and i are both +1, the output of one of the two-terminal and gating circuits of the mechanization of Equation 12 21. willbe +1 and, since'signal is also +1 the next cl will open the three-terminal and gating circuit and change signal j'to -1. Accordingly, the 7 program is changed to the )8 program, as shown in Fig. 6 and line 7 of the table.

Although quantizer 34 has been illustrated and described as receiving its input signals from three brushes being contacted sequentially by a rotating commutator segment, it will be apparent to those skilled in the art that other means exist for converting angular movement into input signals appropriate for this quantizer. Thus, for example, three magnetic transducers with appropriate amplifying circuits may be subsituted for the brushes illustrated, with segment 24 being replaced by a small the -q and q signalconductors of quantizer 42 must be made.

However, for the purpose of explaining difunction half addition, it will be assumed that the q and q signals, as indicated within the brackets of Figures 7a and 7b are applied to 'the adder so as to be added thereby to signals p and p.

permanent magnet or other appropriate magnetic means. time can never be greater than +1 or less than 1 Likewise, opticalmeans employing three photocells may under the above definition, it is obviously impossible, be utilized, as could cam followers actuated by raised porusing the same timing scale, to add two di-function tions on The P p y 0f the r tating disc. These and signals together and produce a third di-function signal other forms Could be p y Without affecting the whose average value is equal to the actual sum of the tual operation of the quantizer circuit nor departing'from average values f th t dd d 'signals the scope and spirit of the present invention. However, the two di function signals may be added, Although only one commutator segment and insulated as is done by adder 45, so as to obtain one-half their insert have been illustrated, it is apparent that a plurality sum, the addition performing an inherent scaling down of q y Spaced commutator Segments nd ins rts Could of their actual sum by a factor of one-half. This scaling be employed, the length of the insulated insert lying bedown thus makes it possible to represent the sum of the tween any two of such segmentsbeing greater than the instantaneous di-function values of +1 and +1 as an maximum spacing between brushes A and C. This latinstantaneous value of +1, and the sum of -1 and -1 as ter requirement is necessary so that the same contact se- +1. However, since no instantaneous di-function value of quence, as set forth above, will be followed in the actual zero exists, it is apparent that a difiiculty arises when the operation of the device. addition of two instantaneous di-function values which dif- It will also be apparent to those skilled in the art, .that fer, that is, the sum of the values +1 and 1 or'l and quantizer 34 may be used to convert longitudinal as well +1 isrequired. This difficulty is overcome by the adder of as angular movement into a di-function signal which the present invention in producing a +1 value, for exrepresents the direction and magnitude of the movement. ample, during the first timing interval that the signals to be In such an embodiment, the three brushes would lie in added differ and then producing a 1 value during the alignment with the movement of a longitudinally movable next timing interval that the signals differ. In this way, member, the'movable member having alternate commuthe average output di-function signal value, when contator segments and insulated portions positioned along the sidered over any two consecutive timing intervals that the alignment of, and contacting the brushes. input di-function signals dilfer, is always equal to :zero,

As will be apparent to those skilled in the art, other the desired value. quantizers, similar to quantizer 34 may be designed with- The circuitry of Figures 7a and 7b are mechanizations out departing from the spirit and the scope of this inof a group of Boolean equations, which equations are vention by arbitrarily designing the programs thereof to derived from a programming table as set forth below in correspond to other sets of brush contact sequences. Table II.

Programming Table 11 L Program Case 1 Case 2 To Generate-0ase 1 To Generate-Case 2 p q d e 8 S Z9 Sd Zn Se Zn Sn Zd 1 -1 I -1 1 .t 1 -1 +1 -1 1 1 1 +1 -1 Y -1 +1 1 1 1 1 +1 +1 +1 -1 1 1 1 1 -1 -1 1 +1 1 1 1 1 -1 +1 +1 -1 1 1 1 1 +1 1 +1 +1 1 1 +1 +1 +1 +1 1 1 As will be apparent from the logic of quantizer 34, the As will be observed from Fig. 7a, half-adder 45 cononlyrequirement for successful operation thereof is that tains a programming or memory electronic switch, such as each brush-commutator segment contact be maintained flip-flop D, and an adder electronic switch, such as flipfor at least two timing intervals. If this condition is fulflop E, the half-adder output signals a and 2' being the filled, then the appropriate flip-flops are triggered and output signals produced by flip-flop E. Flipeflop D prowill not again be triggered until another brush is conduces output signals (1 and d, the conduction state of tacted. Hence, once a satisfactory contact is made, the Tflip-floplD serving, in a sense, as a memory for providing given brush may bounce into. and out of contact with the proper triggering sequence for flip-flop E during the timdisc, or may engage and disengage the commutator seging intervals that theinstantaneous di-function values of ment without causing spurious operation of the quantizer. in ut signals p and q differ. This memory-is primarily Referring now to Figures 7a and 712, there is illusnecessary since p and q may differ in value during a trated in detailed form a pair of di-function half-adders given time interval and then not diifer again until several or averagers accordingto the present invention. As was timing intervals later. Thus, in order that an average stated in connection with Fig. 'l, a di-function subvalue of Zero be generated for these two spaced timing traction between signals p and q was required and, to intervals, it is necessary to remember between them the accomplishthis, a reversal of the input connections of instantaneous value of output signal e during the first timing interval, so that flip-flop E may be triggered to produce the other instantantous value of signal e during the second interval.

In Table II, all possible combinations of values of signals p, q and d are set forth in columns 1, 2 and 3, respectively, on lines 1 through 8. For example, on lines 1 and 2, where p and q are both equal to 1, d may be equal to either 1, as on line 1, or +1 as on line 2. The values of e in Case 1 as presented in column 4, or Case 2 as presented in column 5, is equal to 1, on lines 1 and 2 or one-half of the sum of p=1 and q=l. Also, on lines 7 and 8, e is equal to +1, in both cases, corresponding to one-half the sum of p:+1 and q=+l. The value of d is immaterial for these sets of values of p and q since e is always equal to one-half their sum.

However, the value of d becomes important as a memory signal on each of lines 3 through 6 where the values of p and q differ. In Case 1, e is arbitrarily set equal to 1 on line 3 whenever signals p, q and d are equal to +1, +1 and +1, respectively, and is set equal to +1, +1, and +1 on lines 4, 5 and 6, respectively, in accordance with the values of signals p, q and d contained thereon.

In Case 2, e is arbitrarily set equal to +1 for the values of p, q and a defined on line 3 and is set equal to +1, 1 and +1 on lines 4, 5 and 6, respectively. As is apparent, Cases 1 and 2 define the only two possible arbitrary sets of values that e may take when the values of p and q differ.

There is found in columns 6, 7, 8 and 9 of Table II, the triggering signals to be applied to S Z 8,; and Z input conductors, respectively, of flip-flops E and D for Case 1. For each of the S and Z conductors, a signal is always applied thereto in order to produce the value of e indicated in column 4. Thus, on the simultaneous appearance of the values of p, q and d as found on lines 1 through 3 and 5 where e is equal to 1, a signal is to be applied to the Z conductor in order to make e=1. In the same manner, a signal is to be applied to the S input conductor in order to make e=+1 each instance, as indicated on lines 4 and 6 through 8, the value of e is equal to +1.

In considering the signals to be applied to the S and Z conductors, as has been stated, the value of d is immaterial when both of signals p and q are either +1 or +1 as indicated on lines 1, 2, 7 and 8 since the value of e produced during such instances will always be onehalf of the sum thereof. Thus, consideration must be given to the triggering of flip-flop D only during the timing intervals, as set forth on lines 3 through 6, that the values of p and q differ.

Stated briefly, at the appearance of any of the combinations of values of signals p, q and d set forth on lines 3 through 6, flip-flop D is to be triggered at the beginning of the next timing interval into its other conduction state. If this is done, then the next value of e produced during the next timing interval that p and q differ will be of opposite value than was its value during the first mentioned timing interval. This is true since, as has been stated, the value of d is not changed during the programs set forth on lines 1, 2, 7 and 8 when the values of p and q are identical. Thus, each change of d will remain until the next occurrence of a difference in the p and q signal values.

From the Case 1 programs found in columns 7 through 9 of Table H, and including timing signal cl from source 44, the Boolean equations defining the desired programming of flip-flops D and E may be Written and reduced to:

In setting forth the Boolean equations defining the programming indicated in columns 10 through 13 for the Case 2 example, it will be observed that the triggering signals applied to the 8, and Z conductors of flipflop D are identical to the Case 1 example given above. This is due to the fact that the values signal d takes, as set forth, in the third column upon the various possible combinations of signals p and q, are equally applicable to both cases since the cases differ only in the values assigned to signal e. Accordingly, Equations 15 and 16 apply also to the Case 2 example, and the only new equations that need be written for this case are the ones for S and Z These from columns 10 and 11 may be reduced to:

(Eq. 19) (Eq. 20)

The half-adder circuit of Fig. 7a is a mechanization of Equations 15, 16, 17 and 18, the mechanization being effected in the manner set forth previously in connection with Figures 2 and 3. However, as has been stated, it is desired to utilize adder 45 in the device of Fig. 1, to produce an output signal whose di-function value is a difference between the di-function values of signals p and q. Thus, the operation of di-function subtraction is necessary and is performed by circuit 45 by interchanging the q and q input signals such that the signal p is added to signal q, the complement of signal q.

Consider now the mechanization of Equations 15 through 18 shown in Fig. 7a. More particularly, con sider first Equations 15 and 16 which define the S and Z signals, respectively, for flip-flop D. It will be noted that Equation 15 includes one and operation including three factors, namely, d, cl, and the output of an or" function. The or function includes two terms both of which are outputs of and functions. Accordingly, Equation 15 is mechanized in Fig. 7a by one three terminal and gating circuit receiving signals d, cl and the output of a two-terminal or gating circuit which, in turn, receives the output signals of two two-terminal and gating circuits. One of the two-terminal and gating circuits receives signals p and q, while the other two-terminal and gating circuit receives signals p and q.

In connection with the mechanization of Equation 16, it should be noted that this equation differs from Equation 15 only in the use of signal at rather than signal d. For simplicity of circuitry, therefore, the mechanization of Equation 16 in Fig. 7a utilizes the same or gating circuit and two-terminal and" gating circuits as those utilized for Equation 15. In addition the mechanization of Equation 16 includes a three-terminal and gating circuit receiving signals d, cl and the output of the or gating circuit.

Equation 17, which defines the S signal for flip-flop E includes a two-terminal and gating circuit receiving signal cl and the output of a three-terminal or gating circuit which, in turn, receives the outputs of three two-terminal and gating circuits. The inputs to the three and gating circuits are, reading from top to bottom in Fig. 7a: signals d and q; signals 1 and q; and signals d and p. The mechanization of Equation 18 includes exactly the same number and type of gating circuits as that of Equation 17, except that the input signals to the two-terminal and gating circuits are different. More particularly, the inputs to the three circuits in the mechanization of Equation 18 are, reading from top to bottom: signals p and q; p and d; and q and d.

Consider now the operation of the adder of Fig. 7a in response to input difunction signal trains p and q having values of 4 and respectively. As noted above, adder 45 operates to subtract signal train q from signal train p by adding complementary signal train q to signal train p, signal train q having a value of /4. Accordingly, assuming that signal d is initially 1,

As shown in the table, during the first time interval signals p and q are different and the output of the or gating circuit for 8, and Z is high. Since d is assumed to be 1 (and d=+1) for this interval, the final and gating circuit for S is opened and flip-flop D triggered to set d to +1 in the second time interval. On the other hand, since signals q and dare both +1 during the'first time interval, the top two-terminal and gating circuit for Z is opened and signal e becomes 1 in the second time interval.

Consider now the values of S and Z during the remaining time intervals of the table. During the second, fourth, fifth, seventh and eighth time intervals, signals 2 and q are different. Accordingly, the output of the or gating circuit of S and Z, is high during these intervals, and the state of flip-flop D is reversed. In other words, signal d during the third, fifth, sixth, eighth and ninth intervals is the complement of signal d during the second, fourth, fifth, seventh and eighth intervals. On the other hand, during the third and sixth intervals, signals p and q are both +1. Accordingly, the or gating circuit remains closed during these intervals and signal d is unchanged.

Consider now the values of S and Z during the remaining intervals of the table. Signals q and d during the fourth and seventh intervals are identical to q and d during the first interval. Accordingly Z is opened during the fourth and seventh intervals, and signal e becomes +1 in the fifth and eighth intervals. During the third and sixth intervals, signals p and q are both +1. Under these conditions, the middle two-terminal and gating circuit for S is opened and signal e becomes +1 in the fourth and seventh intervals. During the second and fifth intervals, signals p and d are both +1 and the bottom two-terminal and gating circuit of S is opened resulting in signal e=+1 in the third and sixth intervals. Finally, during the eighth interval, signals q and d are both +1, and the top two-terminal and gating circuit of S is opened resulting in signal e=+1 in the ninth interval.

Summarizing the operation, signal e contains five +s and three +s having an average value of This value of A is equal to one-half the average of the values of signal trains p and q or one-half the difference between the values of signal trains p and q.

The half-adder circuit of Fig. 7b is a mechanization of Equations 15, 16, 19 and 20 as derived from Case 2 of Table II. Since the mechanizations for S and Z in Fig. 7b are identical to those for Fig. 7a no further explanation is required. In addition, it Will be noted that Equations 19 and 20 differ from Equations 17 and 18, respectively, only in the complementing of signal a. Accordingly, the mechanization of these equations in Fig. 7b is identical to the S and Z mechanizations in Fig. 7a except for the substitution of signals d and d for signals d and d, respectively. In operation, the adders of Figs. 7a and 7b respond identically to like input signals, in the manner set forth above. In addition, the response of flip-flop D in both adders is identical for all input signals. The effect of the complementing of signal d in Fig. 7b results in the complementing of signal e when the input signals are different, that is in the second, third, fifth, sixth, eighth and ninth intervals of the example set forth above. In other words, the signal train e produced by the adder of Fig. 7b in response to the input signal trains of the example would be +1, 1, +1, +1, +1, +1, +1, +1 which has an average value of or As is apparent, both of the circuits of Figures 7a and 7b perform di-function half-addition in the manner previously defined.

An operational feature of adder 45 to be considered is that, assuming signal q to have an average value of zero, for example, output signal e will contain only one extra +1 value for each two extra +1 values contained in signal p, signal p normally having alternate +1 and 1 values. Also, if signal 7 contains an extra +1 value and signal q contains an extra +1 value, owing to the subtraction, output signal e will contain only one extra +1 value. This feature of the circuits operation, that is, signal e containing only one extra +1 value or +1 value for each two of such values contained in either of the input signals thereto, is a result of its scaling down or averaging effect on the two input signals.

Referring now to Fig. 8, there is illustrated deconverter 46 in block schematic form. Deconverter 46 produces a pair of output signals on its output conductors 47 and 48 which represent in voltage level form the same information as that possessed by the half-adder output signal e indi-function form.

In particular, deconverter 46 produces a high voltage level on output conductor 47 each timing interval that signal e contains an extra +1 value and produces a high voltage level on conductor 48 for each timing interval signal e contains an extra +1 value, the extra +1 and +1 values occurring during a sequence of alternate +1 and +1 values representing an average di-function value of zero.

Deconverter 46 contains an electronic switch, such as flip-flop F, producing a'pair of complementary output signals f and f and, in order to accomplish the desired deconversion in the above stated manner, flip-flop F must be coupled to flip-flop B so as to form with it a twostage shifting register circuit. With this done, each successive value of signal e is, during the next timing interval, transferred to signal 7 with the result that each two adjacent di-function values of signal a may be compared. Thus, if signals e and 1 both have +1 values, a high voltage level is produced on conductor 47 to indicate thereby that signal e contains an extra +1 value. On the other hand, if signals e and each have a +1 value, a high voltage level is produced on output conductor 48 to indicate thereby the extra 1 value in signal e.

Although the circuitry to accomplish the above stated results may be drawn by inspection, a Table III, from which are derived the Boolean equations defining the circuitry of Fig. 8, is included below.

Programming T able. III

Flip-Flop Output Signals To Line Generate In columns 1 and 2 of Table III are found the four possible combinations of values that signals e and [may have as indicated on lines 1 through 4, respectively.

In column 3'are found the values to be generated at the beginning of the'next timing interval for signal 1 in order to provide the stated shifting register opera- (tion. On each line signal 1 is to be made equal, at the beginning of the next timing interval, to the value thereon given for signal e.

From column 3, the equations for the signals to be applied to the S and Z, input conductors of flip-flop F may be written and simplified to:

In column 4, line 1 of Table II is found the program when, by definition, a +1 output signal is to appear on conductor 47 while in column 5, line 4, is found the program when, by definition, a -1 output signal is to appear on conductor 48. This is true since on line 1, e and f are both equal to +1 and on line 4, e and f are both equal to 1. The Boolean equations defining these output signals may be written and reduced to:

The circuitry illustrated in Fig. 8 is the mechanization of Equations 21 through 24, with Equation 23 being represented by and gating circuit 162 and Equation 24 being represented by and gating circuit 164. The operation of deconverter 46 may be most readily understood by reference to the composite group of signal waveforms illustrated in Fig. 9 and taken by way of example.

Here, timing signal 100 is again illustrated while output signal e, generally designated 150 in Fig. 9, is illustrated as is its complementary signal e, generally designated 152 in Fig. 9. Signal 1, generally designated 154 in Fig. 9 is identical to signal 150 but is delayed one timing interval to the right, as viewed from Fig. 9, from signal 150. In the same manner, signal f, generally deisgnated 156 in Fig. 9, is identical to, but delayed one timing interval, from signal 152.

During the first timing interval, signals 150 and 154 are at their low and high voltage levels, respectively, with the result that the signal, generally designated 158 in Fig. 9, appearing on output conductor 47 is at its low voltage level owing to the action of the and gating circuit 162 to which signals 150 and 154 are applied. At the beginning of the second timing interval, each of signals 150 and 154 switch their conduction states and signal 158 still remains at its low voltage level.

However, during the third timing interval, signal 150 remains at its high voltage level and thus contains two consecutive high voltage levels. Signal 154 during the third timing interval is also at its high voltage level, which voltage level corresponds to the high voltage level of signal 150 appearing during the second timing interval. Thus, signal 158 contains a high voltage level during the third timing interval owing to the action of and gating circuit 162 and thus indicates on conductor 147, the extra +1 value of signal 150 produced during the third timing interval.

During the sixth and seventh timing intervals, signal 150 contains two adjacent low voltage levels with the result that signals 152 and 156 are at their high voltage levels during the seventh timing interval. This results in the signal, generally designated 160 in Fig. 9, appearing on output conductor 48, containing a high voltage level during this interval owing to the action of the and gating circuit 164 to which signals 152 and 156 are applied.

The action of deconverter 46 during the remaining timing intervals indicated in Fig. 9 may be readily understood from the description presented above.

As will be apparent to those skilled in the art, output signals 158 and 160 could readily be produced by a pair of flip-flops, respectively, rather than gating circuits 162 and 164 as is here illustrated. Such fiipeflops would be triggered through gating circuits employing as input 28 signals, signals 150, 152, 154 and 156 and their output signals would correspond in form to signals 158 and 160 but delayed one interval therefrom owing to the required triggering operation.

Having thus described in detail quantizer 34, adder 45 and deconverter 46, reference is again made to the operation of the system. of Fig. 1. There is illustrated in Fig. 10 a composite group of signal wavefonns, taken by way of example, of signals appearing at various points in the circuit of Fig. 1. Thus, timing signal is again illustrated and output signal train p, generally designated 166 in Fig. 10, of quantizer 34 discloses extra -1 and +1 values during the seventh and seventeenth timing intervals, respectively, to indicate complete revolutions of shaft 20 in the negative and positive directions, respectively. Output signal train q, generally designated 168 in Fig. 10, of quantizer 42, disclosed extra +1 and 1 values during the fourth and fourteenth timing intervals, respectively, to indicate complete revolutions of shaft 36 in positive and negative directions, respectively. Signal train q, generally designated 170 in Fig. 10, is complementary to signal train 168 and thus contains extra -1 and +1 values during the fourth and fourteenth timing intervals, respectively.

As has been stated, owing to the reverse connections of signals 168 and 170 to adder 45, complementary signal 170 is added to signal train 166 with the result that output signal e, again designated 150, of adder 45 is the di-function subtraction of signal train 168 from signal train 166. For purposes of explanation, signal train is shown as aligned with trains 166 and 170, rather than displaced one timing interval as in the actual operation of the adders of Figs. 7a and 7b. As will be observed, during the 1st timing interval, signals 170 and 166 differ in value and for the purposes of this explanation, the sum thereof is arbitrarily set equal to a +1 value as indicated in signal train 150. With this first value established, signal train 150 contains during the remaining timing intervals that signals 170 and 166 differ in value, alternate 1 and +1 values.

By inspection, it is seen that the di-function addition of signal train 170 and 166 will produce in signal train 150, an extra 1 value during the seventh timing interval and an extra +1 value during the seventeenth timing interval. The extra 1 value of signal train 150 appearing during the seventh timing interval will, in the manner explained for the operation of deconverter 46, produce during this seventh timing interval, a high voltage level in the deconverters output signal, again designated 160, appearing on output conductor 48. Also, the extra +1 value of signal train 150 will produce during the seventeenth timing interval a high voltage level in the deconverters output signal, again designated 158, appearing on output conductor 47.

Differentiating circuit 47a will differentiate signal 158 and the differentiated result thereof is illustrated by the signal, generally designated 158a in Fig. 10, while the signal produced by the differentiation of signal by differentiating circuit 48a is illustrated by the signal, generally designated 160a in Fig. 10.

In the manner explained previously for the operation of counter 49,- the negative pulse appearing in signal 160a at the beginning of the eighth timing interval will cause counter 49 to reduce its binary count by one binary digit. If, for example, counter 49 contains four stages and has an initial count of 0000, as designated 172 in Fig. 10, this negative pulse of signal 160a will reduce the count of counter 49 by one binary digit to 1111.

The positive pulse of signal 158a appearing at the beginning of the seventeenth timing interval causes counter 49 to increase its count by one binary digit. Thus, the then existing count of 1111 will be increased by one binary digit to its initial value of 0000 as indicated in count 172.

As was stated previously, adder 45 produces an extra 

